1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a gate structure and a method of fabricating the same.
2. Description of the Related Art
In most conventional semiconductor process, silicon oxide (SiO2) is used to form the gate dielectric layer. With the rapid progress in the integrated circuit manufacturing industry, the design of circuit devices increasingly depends on miniaturization to increase the level of device integration and the driving capability of the devices. As the line width of gates is reduced, thickness of the gate dielectric layer must be reduced correspondingly. As a result, the chance of having a direct tunneling will increase leading to a rapid increase in the leakage current. To resolve this problem, a dielectric layer fabricated using a high dielectric constant (K) is demanded.
However, the integration of a high-K dielectric layer with transistors often encounters some technical difficulties because the use of a high-K material often results in a drop in mobility and device reliability. Moreover, as the thickness of the gate dielectric layer decreases, the phenomena of boron penetration and polysilicon gate depletion intensify. Boron penetration can be ameliorated through doping a small amount of nitrogen in the oxide layer. However, the effect of polysilicon gate depletion can hardly be avoided. Furthermore, the deployment of a high-K dielectric layer tends to increase the threshold voltage of a device and prevents the integration of the high-K dielectric layer with a polysilicon gate. Therefore, the method of replacing the polysilicon with a metal gate is proposed. Aside from avoiding polysilicon gate depletion, the metal gate can also lower parasitic resistance in the gate.
Yet, most gate structures comprising a high-K dielectric layer and a metal gate have poor dielectric layer/silicon substrate interface properties that will affect the operation and performance of the device.